Electrostatic discharge (ESD) voltage and current can be a major source of damage for integrated circuits. ESD can be a problem with an integrated circuit that is not in operation or coupled to a circuit. At these times, many of the integrated circuit's external connections are floating and exposed to damage. The potential for ESD damage has become even more of a predominant issue with the decreasing device sizes, spacing, and operating voltages of modern components, all of which has the effect of increasing the likelihood of an ESD event causing damage.
The primary object of most common types of ESD protection is to isolate vulnerable internal circuitry from an ESD event. An integrated circuit connects to its external environment through interconnect pads (also referred to as die terminals, bond pads, die pads, or contact pads). Typically an ESD protection circuit is incorporated at, or shortly after, the interconnect pad in an integrated circuit and contains breakdown devices and current limiting devices that provide an alternative and more durable path for the damaging ESD voltage and current to flow through. ESD protection circuitry, however, while necessary for ESD event survival, can interfere with signal transmission speed and increase capacitive loading when the integrated circuit is operation. Therefore in ESD protection circuitry a balance is sought which preserves signal speed while not over exposing the integrated circuit to damage from ESD.
Various techniques have been utilized in constructing ESD protection circuits for integrated circuits and are well know to those skilled in the art. One such common ESD technique is to incorporate an input buffer of more durable circuit components between the interconnect pad and the internal active circuitry that is capable of better absorbing the elevated potentials of a given ESD event. However, these heavier duty components typically also have a higher input drive requirements and corresponding signal propagation delays that can become unacceptable to the design specifications of the integrated circuit. Another technique is to incorporate one or more clamping diodes or other such breakdown circuits that couple an ESD event to a discharge path away from the more damage susceptible input components. A further technique is to incorporate “guard rings” of opposite carrier, or over doped similar carrier, semiconductor that form a protecting diode or conduction path system around the input circuitry and interconnect pads.
A common ESD protection technique is to incorporate a resistance into the integrated circuit input just after the interconnect pad. One of the effects of this input resistance has is to current limit the ESD event. An ESD damping input resistance incorporated at the interconnect pad helps dissipate an ESD event quickly and contain it near the interconnect pad. Unfortunately, this technique can cause a significant signal propagation delay issue by adding a higher RC time constant when the ESD input resistance is combined with the capacitive load of the input circuit and interconnect line. Unless the external drive of the integrated circuit input is made larger, it now will take longer to charge the input interconnect's capacitive load through the ESD protection resistance. The reduction in device and feature size in modern integrated circuits has increased resistance of the interconnect lines themselves to become a significant factor in the total input resistance. These interconnect line resistances add to the ESD resistance giving a larger effective input resistance than intended. Furthermore, the interconnect resistances tend to be of variable size, as the input interconnect lines are of differing lengths and cross section. This leads to issues of varying RC time delay on different input lines, a significant issue in high speed and synchronous design.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to reduce signal delay from ESD. Additionally there is a need for the ability to have matched delays or resistances across inputs.